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? semiconductor components industries, llc, 2012 may, 2012 ? rev. 1 1 publication order number: PCA9655E/d PCA9655E remote 16-bit i/o expander for i 2 c bus with interrupt the PCA9655E provides 16 bits of general purpose parallel input / output (gpio) expansion through the i 2 c ? bus / smbus. the PCA9655E consists of two 8 ? bit configuration (input or output selection); input, output and polarity inversion (active ? high or active ? low operation) registers. at power on, all i/os default to inputs. each i/o may be configured as either input or output by writing to its corresponding i/o configuration bit. the data for each input or output is kept in its corresponding input or output register. the polarity inversion register may be used to invert the polarity of the read register. all registers can be read by the system master. the PCA9655E provides an open ? drain interrupt output which is activated when any input state differs from its corresponding input port register state. the interrupt output is used to indicate to the system master that an input state has changed. the power ? on reset sets the registers to their default values and initializes the device state machine. three hardware pins (ad0, ad1, ad2) are used to configure the i 2 c ? bus slave address of the device. up to 64 devices are allowed to share the same i 2 c ? bus / smbus. features ? v dd operating range: 1.65 v to 5.5 v ? sda sink capability: 30 ma ? 5.5 v tolerant i/os ? polarity inversion register ? active low interrupt output ? low standby current ? noise filter on scl/sda inputs ? no glitch on power ? up ? internal power ? on reset ? 64 programmable slave addresses using three address pins ? 16 i/o pins which default to 16 inputs ? i 2 c scl clock frequencies supported: standard mode: 100 khz fast mode: 400 khz fast mode +: 1 mhz ? esd performance: 2000 v human body model, 200 v machine model ? these are pb ? free devices soic ? 24 dw suffix case 751e see detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. ordering information marking diagrams http://onsemi.com tssop ? 24 dt suffix case 948h 1 wqfn24 mt suffix case 485bg pca 9655e alyw pca96 55eg awlyyww PCA9655E awlyywwg xxxx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb ? free package (note: microdot may be in either location)
PCA9655E http://onsemi.com 2 block diagram remark: all i/os are set as inputs at reset. figure 1. block diagram figure 2. simplified schematic of i/os PCA9655E power ? on reset i 2 c ? bus/smbus control input filter scl sda v dd input/ output ports io0_0 v ss 8 ? bit write pulse read pulse io0_2 io0_1 io0_3 io0_4 io0_5 io0_6 io0_7 input/ output ports io1_0 8 ? bit write pulse read pulse io1_2 io1_1 io1_3 io1_4 io1_5 io1_6 io1_7 int ad1 ad0 ad2 lp filter v dd at power ? on reset, all registers return to default values. v dd i/o pin output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data polarity inversion register data ff data from shift register ff ff ff q1 q2 v ss to int 100 k
PCA9655E http://onsemi.com 3 pin assignment figure 3. soic24 / tssop24 figure 4. wqfn24 (the exposed thermal pad at the bottom is not connected to internal circuitry) v int dd sda ad1 scl ad2 ad0 io0_0 io1_7 io0_1 io1_6 io0_2 io1_5 io0_3 io1_4 io0_4 io1_3 io0_5 io1_2 io0_6 io1_1 io0_7 v ss io1_0 PCA9655E 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 transparent top view io1_3 io1_4 io0_3 io0_2 io0_1 ad0 io0_0 io0_6 io0_7 v ss io1_0 io1_1 io1_2 ad2 ad1 int v dd sda scl terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 PCA9655E io0_5 io0_4 io1_5 io1_6 io1_7 table 1. pin descriptions symbol pin description soic24, tssop24 wqfn24 int 1 22 interrupt output (active ? low) ad1 2 23 address input 1 ad2 3 24 address input 2 io0_0 4 1 port 0 i/o 0 io0_1 5 2 port 0 i/o 1 io0_2 6 3 port 0 i/o 2 io0_3 7 4 port 0 i/o 3 io0_4 9 5 port 0 i/o 4 io0_5 9 6 port 0 i/o 5 io0_6 10 7 port 0 i/o 6 io0_7 11 9 port 0 i/o 7 v ss 12 9 supply ground io1_0 13 10 port 1 i/o 0 io1_1 14 11 port 1 i/o 1 io1_2 15 12 port 1 i/o 2 io1_3 16 13 port 1 i/o 3 io1_4 17 14 port 1 i/o 4 io1_5 18 15 port 1 i/o 5 io1_6 19 16 port 1 i/o 6 io1_7 20 17 port 1 i/o 7 ad0 21 18 address input 0 scl 22 19 serial clock line sda 23 20 serial data line v dd 24 21 supply voltage
PCA9655E http://onsemi.com 4 table 2. maximum ratings symbol parameter value unit v dd dc supply voltage ? 0.5 to +7.0 v v i/o input / output pin voltage ? 0.5 to +7.0 v i i input current 20 ma i o output current 50 ma i dd dc supply current 100 ma i gnd dc ground current 600 ma p tot total power dissipation 600 mw p out power dissipation per output 200 mw t stg storage temperature range ? 65 to +150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance (note 1) soic ? 24 tssop ? 24 wqfn24 85 91 68 c/w msl moisture sensitivity level 1 f r flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in v esd esd withstand voltage human body model (note 2) machine model (note 3) > 2000 > 200 v i latchup latchup performance above v dd and below gnd at 125 c (note 4) 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. measured with minimum pad spacing on an fr4 board, using 10 mm ? by ? 1 inch, 2 ounce copper trace no air flow. 2. tested to eia / jesd22 ? a114 ? a. 3. tested to eia / jesd22 ? a115 ? a. 4. tested to eia / jesd78. table 3. recommended operating conditions symbol parameter min max unit v dd positive dc supply voltage 1.65 5.5 v v i/o switch input / output voltage 0 5.5 v t a operating free ? air temperature ? 55 +125 c t / v input transition rise or fall rate 0 5 ns/v
PCA9655E http://onsemi.com 5 table 4. dc electrical characteristics v dd = 1.65 v to 5.5 v, unless otherwise specified. symbol parameter conditions t a = ? 55 c to +125 c unit min typ max supplies i stb standby current standby mode; no load; v i = 0 v; f scl = 0 hz; i/o = inputs v i = v dd ; f scl = 0 hz; i/o = inputs 1.1 0.25 1.5 1 ma a v por power ? on reset voltage (note 5) 1.5 1.65 v input scl; input / output sda v ih high ? level input voltage 0.7 x v dd v v il low ? level input voltage 0.3 x v dd v i ol low ? level output current v ol = 0.4 v; v dd < 2.3 v 10 ma v dd 2.3 v 20 i l leakage current v i = v dd or 0 v 1 a c i input capacitance v i = 0 v 4.6 6 pf i/os v ih high ? level input voltage 0.7 x v dd v v il low ? level input voltage 0.3 x v dd v i ol low ? level output current (note 6) v ol = 0.5 v; v dd = 1.65 v v ol = 0.5 v; v dd = 2.3 v v ol = 0.5 v; v dd = 3.0 v v ol = 0.5 v; v dd = 4.5 v 8 12 17 25 20 28 35 42 ma i ol(tot) total low ? level output current (note 6) v ol = 0.5 v; v dd = 4.5 v 400 ma v oh high ? level output voltage i oh = ? 3 ma; v dd = 1.65 v i oh = ? 4 ma; v dd = 1.65 v i oh = ? 8 ma; v dd = 2.3 v i oh = ? 10 ma; v dd = 2.3 v i oh = ? 8 ma; v dd = 3.0 v i oh = ? 10 ma; v dd = 3.0 v i oh = ? 8 ma; v dd = 4.5 v i oh = ? 10 ma; v dd = 4.5 v 1.2 1.1 1.8 1.7 2.6 2.5 4.1 4.0 v i lh input leakage current v dd = 5.5 v; v i = v dd 1 a i ll input leakage current v dd = 5.5 v; v i = 0 v ? 100 a c i/o input / output capacitance (note 7) 5.0 6.0 pf interrupt (int ) i ol low ? level output current v ol = 0.4 v 6.0 ma c o output capacitance 5.0 5.5 pf inputs ad0, ad1, ad2 v ih high ? level input voltage 0.7 x v dd v v il low ? level input voltage 0.3 x v dd v i l leakage current v i = v dd or 0 v 1 a c i input capacitance 4.5 5.0 pf 5. the power ? on reset circuit resets the i 2 c bus logic with v dd < v por and set all i/os to logic 1 upon power ? up. thereafter, v dd must be lower than 0.2 v to reset the part. 6. each bit must be limited to a maximum of 25 ma and the total package limited to 400 ma due to internal bussing limits. 7. the value is not tested, but verified on sampling basis.
PCA9655E http://onsemi.com 6 table 5. ac electrical characteristics v dd = 1.65 v to 5.5 v; t a = ? 55 c to +125 c, unless otherwise specified. symbol parameter standard mode fast mode fast mode + unit min max min max min max f scl scl clock frequency 0 0.1 0 0.4 0 1.0 mhz t buf bus ? free time between a stop and start condition 4.7 1.3 0.5 s t hd:sta hold time (repeated) start condition 4.0 0.6 0.26 s t su:sta setup time for a repeated start condition 4.7 0.6 0.26 s t su:sto setup time for stop condition 4.0 0.6 0.26 s t hd:dat data hold time 0 0 0 ns t vd:ack data valid acknowledge time (note 8) 0.3 3.45 0.1 0.9 0.05 0.45 s t vd:dat data valid time (note 9) 300 50 50 450 ns t su:dat data setup time 250 100 50 ns t low low period of scl 4.7 1.3 0.5 s t high high period of scl 4.0 0.6 0.26 s t f fall time of sda and scl (notes 11 and 12) 300 20 + 0.1c b (note 10) 300 120 ns t r rise time of sda and scl 1000 20 + 0.1c b (note 10) 300 120 ns t sp pulse width of spikes suppressed by input filter (note 13) 50 50 50 ns port timing: c l 100 pf (see figures 6, 9 and 10) t v(q) data output valid time (v dd = 4.5 v to 5.5 v) (v dd = 2.3 v to 4.5 v) (v dd = 1.65 v to 2.3 v) 200 350 550 200 350 550 200 350 550 ns t su(d) data input setup time 100 100 100 ns t h(d) data input hold time 1 1 1 s interrupt timing: c l 100 pf (see figures 9 and 10) t v(int_n) data valid time 4 4 4 s t rst(int_n) reset delay time 4 4 4 s 8. t vd:ack = time for acknowledgment signal from scl low to sda (out) low. 9. t vd:dat = minimum time for sda data out to be valid following scl low. 10. c b = total capacitance of one bus line in pf. 11. a master device must internally provide a hold time of al least 300 ns for the sda signal (refer to v il of the scl signal) in order to bridge the undefined region scl?s falling edge. 12. the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines without exce eding the maximum specified t f . 13. input filters on the sda and scl inputs suppress noise spikes less than 50 ns.
PCA9655E http://onsemi.com 7 device address before the bus master can access a slave device, it must send the address of the slave it is accessing and the operation it wants to perform (read or write) following a start condition. the slave address of the PCA9655E is shown in figure 5. address pins ad2, ad1, and ad0 choose 1 of 64 slave addresses. to conserve power, no internal pull ? up resistors are provided on ad2, ad1, and ad0. a logic 1 on the last bit of the first byte selects a read operation while a logic 0 selects a write operation. figure 5. PCA9655E device address r/w a6 a5 a4 a3 a2 a1 a0 programmable slave address table 6. PCA9655E address map address input slave address ad2 ad1 ad0 a6 a5 a4 a3 a2 a1 a0 hex gnd scl gnd 0 0 1 0 0 0 0 20h gnd scl vdd 0 0 1 0 0 0 1 22h gnd sda gnd 0 0 1 0 0 1 0 24h gnd sda vdd 0 0 1 0 0 1 1 26h vdd scl gnd 0 0 1 0 1 0 0 28h vdd scl vdd 0 0 1 0 1 0 1 2ah vdd sda gnd 0 0 1 0 1 1 0 2ch vdd sda vdd 0 0 1 0 1 1 1 2eh gnd scl scl 0 0 1 1 0 0 0 30h gnd scl sda 0 0 1 1 0 0 1 32h gnd sda scl 0 0 1 1 0 1 0 34h gnd sda sda 0 0 1 1 0 1 1 36h vdd scl scl 0 0 1 1 1 0 0 38h vdd scl sda 0 0 1 1 1 0 1 3ah vdd sda scl 0 0 1 1 1 1 0 3ch vdd sda sda 0 0 1 1 1 1 1 3eh gnd gnd gnd 0 1 0 0 0 0 0 40h gnd gnd vdd 0 1 0 0 0 0 1 42h gnd vdd gnd 0 1 0 0 0 1 0 44h gnd vdd vdd 0 1 0 0 0 1 1 46h vdd gnd gnd 0 1 0 0 1 0 0 48h vdd gnd vdd 0 1 0 0 1 0 1 4ah vdd vdd gnd 0 1 0 0 1 1 0 4ch vdd vdd vdd 0 1 0 0 1 1 1 4eh gnd gnd scl 0 1 0 1 0 0 0 50h gnd gnd sda 0 1 0 1 0 0 1 52h gnd vdd scl 0 1 0 1 0 1 0 54h gnd vdd sda 0 1 0 1 0 1 1 56h vdd gnd scl 0 1 0 1 1 0 0 58h vdd gnd sda 0 1 0 1 1 0 1 5ah vdd vdd scl 0 1 0 1 1 1 0 5ch vdd vdd sda 0 1 0 1 1 1 1 5eh
PCA9655E http://onsemi.com 8 table 6. PCA9655E address map slave address address input hex a0 a1 a2 a3 a4 a5 a6 ad0 ad1 ad2 scl scl gnd 1 0 1 0 0 0 0 a0h scl scl vdd 1 0 1 0 0 0 1 a2h scl sda gnd 1 0 1 0 0 1 0 a4h scl sda vdd 1 0 1 0 0 1 1 a6h sda scl gnd 1 0 1 0 1 0 0 a8h sda scl vdd 1 0 1 0 1 0 1 aah sda sda gnd 1 0 1 0 1 1 0 ach sda sda vdd 1 0 1 0 1 1 1 aeh scl scl scl 1 0 1 1 0 0 0 b0h scl scl sda 1 0 1 1 0 0 1 b2h scl sda scl 1 0 1 1 0 1 0 b4h scl sda sda 1 0 1 1 0 1 1 b6h sda scl scl 1 0 1 1 1 0 0 b8h sda scl sda 1 0 1 1 1 0 1 bah sda sda scl 1 0 1 1 1 1 0 bch sda sda sda 1 0 1 1 1 1 1 beh scl gnd gnd 1 1 0 0 0 0 0 c0h scl gnd vdd 1 1 0 0 0 0 1 c2h scl vdd gnd 1 1 0 0 0 1 0 c4h scl vdd vdd 1 1 0 0 0 1 1 c6h sda gnd gnd 1 1 0 0 1 0 0 c8h sda gnd vdd 1 1 0 0 1 0 1 cah sda vdd gnd 1 1 0 0 1 1 0 cch sda vdd vdd 1 1 0 0 1 1 1 ceh scl gnd scl 1 1 1 0 0 0 0 e0h scl gnd sda 1 1 1 0 0 0 1 e2h scl vdd scl 1 1 1 0 0 1 0 e4h scl vdd sda 1 1 1 0 0 1 1 e6h sda gnd scl 1 1 1 0 1 0 0 e8h sda gnd sda 1 1 1 0 1 0 1 eah sda vdd scl 1 1 1 0 1 1 0 ech sda vdd sda 1 1 1 0 1 1 1 eeh
PCA9655E http://onsemi.com 9 registers command byte during a write transmission, the address byte is followed by the command byte. the command byte determines which of the following registers will be written or read. table 7. command byte command register 0 input port 0 1 input port 1 2 output port 0 3 output port 1 4 polarity inversion port 0 5 polarity inversion port 1 6 configuration port 0 7 configuration port 1 registers 0 and 1: input port registers these registers are input ? only. they reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by registers 6 or 7. writes to these registers have no effect. the externally ? applied logic level determines the default value ?x?. table 8. input port 0 register bit 7 6 5 4 3 2 1 0 symbol i0.7 i0.6 i0.5 i0.4 i0.3 i0.2 i0.1 i0.0 default x x x x x x x x table 9. input port 1 register bit 7 6 5 4 3 2 1 0 symbol i1.7 i1.6 i1.5 i1.4 i1.3 i1.2 i1.1 i1.0 default x x x x x x x x registers 2 and 3: output port registers these registers are output ? only. they reflect the outgoing logic levels of the pins defined as outputs by registers 6 and 7. bit values in these registers have no effect on pins defined as inputs. in turn, reads from these registers reflect the values that are in the flip ? flops controlling the output selection, not the actual pin values. table 10. output port 0 register bit 7 6 5 4 3 2 1 0 symbol o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 1 1 1 1 1 1 1 1 table 11. output port 1 register bit 7 6 5 4 3 2 1 0 symbol o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 1 1 1 1 1 1 1 1
PCA9655E http://onsemi.com 10 registers 4 and 5: polarity inversion registers these registers allow the polarity of the data in the input port registers to be inverted. the input port data polarity will be inverted when its corresponding bit in these registers is set (written with ?1?), and retained when the bit is cleared (written with a ?0?). table 12. polarity inversion port 0 register bit 7 6 5 4 3 2 1 0 symbol n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 0 0 0 0 0 0 0 0 table 13. polarity inversion port 1 register bit 7 6 5 4 3 2 1 0 symbol n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 0 0 0 0 0 0 0 0 registers 6 and 7: configuration registers the i/o pin directions are configured through the configuration registers. when a bit in the configuration registers is set (written with ?1?), the bit?s corresponding port pin is enabled as an input with the output driver in high ? impedance. when a bit is cleared (written with ?0?), the corresponding port pin is enabled as an output. note that there is a high value resistor tied to v dd at each pin. at reset, the device?s ports are inputs with a pull ? up to v dd . table 14. configuration port 0 register bit 7 6 5 4 3 2 1 0 symbol c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 1 1 1 1 1 1 1 1 table 15. configuration port 1 register bit 7 6 5 4 3 2 1 0 symbol c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 1 1 1 1 1 1 1 1 power ? on reset upon application of power, an internal power ? on reset (por) holds the PCA9655E in a reset condition while v dd is ramping up. when v dd has reached v por , the reset condition is released and the PCA9655E registers and smbus state machine will initialize to their default states. the reset is typically completed by the por and the part enabled by the time the power supply is above v por . however, when doing a power reset cycle, it is necessary to lower the power supply below 0.2 v, and then restored to the operating voltage. i/o port (see figure 2) when an i/o pin is configured as an input, fets q1 and q2 are off, creating a high ? impedance input with a weak pull ? up (100 k typ) to v dd . the input voltage may be raised above v dd to a maximum of 5.5 v. when the i/o pin is configured as an output, then either q1 or q2 is enabled, depending on the state of the output port register. care should be exercised if an external voltage is applied to an i/o configured as an output because of the low ? impedance path that exists between the pin and either v dd or v ss .
PCA9655E http://onsemi.com 11 bus transactions writing to the port registers to transmit data to the PCA9655E, the bus master must first send the device address with the least significant bit set to logic 0 (see figure 5 ?PCA9655E device address?). the command byte is sent after the address and determines which registers will receive the data following the command byte. there are eight registers within the PCA9655E. these registers are configured to operate as four register pairs: input ports, output ports, polarity inversion ports, and configuration ports. data bytes are sent alternately to each register in a r egister pair (see fi gures 6 and 7). for example, if one byte is sent to output port 1 (register 3), then the next byte will be stored in output port 0 (register 2). there is no limitation on the number of data bytes sent in one write transmission. in this way, each 8 ? bit register may be updated independently of the other registers. figure 6. write to output port registers a2 a1 a0 0 a s a6 start condition r/w acknowledge from slave a scl sda a write to port data out from port 0 p t v(q) 9 8 7 6 5 4 3 2 1 command byte data to port 0 data 0 slave address 0 stop condition 0.0 0.7 acknowledge from slave acknowledge from slave data to port 1 data 1 1.0 1.7 a data out from port 1 t v(q) data valid a5 a4 a3 0 0 0 0 0 1 0 figure 7. write to configuration registers a2 a1 a0 0 a s a6 start condition r/w acknowledge from slave a scl sda ap 9 8 7 6 5 4 3 2 1 command byte data to register data 0 slave address 0 stop condition lsb msb acknowledge from slave acknowledge from slave data to register data 1 lsb msb a a5 a4 a3 0 0 0 1 1 0 0 reading the port registers to read data from the PCA9655E, the bus master must first send the PCA9655E address with the least significant bit set to logic 0 (see figure 5 ?PCA9655E device address?). the command byte is sent after the address and determines which register will be accessed. after a restart, the device address must be sent again, but this time, the least significant bit is set to logic 1. data from the register defined by the command byte will then be sent by the PCA9655E (see figures 8, 9 and 10). data is clocked into the register on the falling edge of the acknowledge clock pulse. after the first byte is read, additional bytes may be read but with data alternately coming from each register in the pair. for example, if you read input port 1, then the next byte read would be input port 0. there is no limitation on the number of data bytes received in one read transmission but the bus master must not acknowledge the data for the final byte received.
PCA9655E http://onsemi.com 12 figure 8. read from register remark: transfer can be stopped at any time by a stop condition. a s start condition r/w acknowledge from slave a acknowledge from slave sda ap acknowledge from master data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) a2 a1 a0 1a a6 r/w acknowledge from slave slave address at this moment master ? transmitter becomes master ? receiver and slave ? receiver becomes slave ? transmitter na no acknowledge from master command byte a2 a1 a0 a6 0 data from lower or upper byte of register lsb msb data (last byte) data from upper or lower byte of register lsb msb a5 a4 a3 a5 a4 a3 figure 9. read from input port register, scenario 1 remark: transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the latest acknowl edge phase is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). a2 a1 a0 1 a s a6 start condition r/w acknowledge from slave a scl sda a read from port 0 p 9 8 7 6 5 4 3 2 1 i0.x slave address 7 stop condition acknowledge from master a i1.x 7 acknowledge from master a i0.x 7 acknowledge from master 1 i1.x 7 non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int_n) t rst(int_n) a5a4a3 654 3210 654 3210 654 3210 654 3210
PCA9655E http://onsemi.com 13 figure 10. read from input port register, scenario 2 remark: transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the latest acknowl edge phase is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). a2 a1 a0 1 a s a6 start condition r/w acknowledge from slave a scl sda a read from port 0 p 9 8 7 6 5 4 3 2 1 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int_n) t rst(int_n) 2 1 a t a d 3 0 a t a d 0 1 a t a d 0 0 a t a d data 00 data 01 t h(d) t h(d) data 02 t su(d) data 03 t su(d) 2 1 a t a d 1 1 a t a d 0 1 a t a d a5a4 a3 interrupt output the open ? drain interrupt output is activated when an i/o pin configured as an input changes state. the interrupt is deactivated when the input pin returns to its previous state or when the input port register is read (see figure 9). a pin configured as an output cannot cause an interrupt. since each 8 ? bit port is read independently, the interrupt caused by port 0 will not be cleared by a read of port 1 or the other way around. remark : changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
PCA9655E http://onsemi.com 14 application information figure 11. typical application device address configured as 0100 000xb for this example. io0_0, io0_2, io0_3 configured as outputs. io0_1, io0_4, io0_5 configured as inputs. io0_6, io0_7, and io1_0 to io1_7 configured as inputs. PCA9655E io0_0 io0_1 scl sda v dd (5 v) master controller int io0_2 v dd ad2 ad1 ad0 v dd gnd int 10 k sub ? system 1 (e.g., temp sensor) io0_3 int sub ? system 2 (e.g., counter) reset controlled switch (e.g., 7sb or fst) v dd a b enable sub ? system 3 (e.g., alarm system) alarm io0_4 io0_5 io0_6 10 digit numeric keypad v ss 10 k 10 k 2 k io0_7 io1_0 io1_1 io1_2 io1_3 io1_4 io1_5 io1_6 io1_7 sda scl characteristics of the i 2 c ? bus the i 2 c ? bus is meant for 2 ? way, 2 ? line communication between different ics or modules. the two lines are the serial data line (sda) and the serial clock line (scl). both lines must be connected to a positive supply via a pull ? up resistor when connected to the output stages of a device. data transfer may only be initiated when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. changes in the data line during the high period of the clock pulse will be interpreted as control signals (see figure 12).
PCA9655E http://onsemi.com 15 figure 12. bit transfer data line stable; data valid change of data allowed sda scl start and stop conditions both data and clock lines remain high when the bus is not busy. a start condition (s) occurs when there is a high ? to ? low transition of the data line while the clock is high. a stop condition (p) occurs when there is a low ? to ? high transition of the data line while the clock is high (see figure 13). figure 13. definition of start and stop conditions sda scl p stop condition sda scl s start condition system configuration a device generating a message is a ?transmitter?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 14). figure 14. system configuration master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c ? bus multiplexer slave acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each 8 ? bit byte is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra clock pulse for the acknowledge bit. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, such that the sda line is stable low during the high period of the acknowledge clock pulse; set ? up time and hold time must be taken into account. a master receiver signals an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition.
PCA9655E http://onsemi.com 16 figure 15. acknowledgement of the i 2 c bus s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master timing and test setup figure 16. definition of timing on the i 2 c bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl figure 17. test circuitry for switching times figure 18. load circuit pulse generator v o c l 50 pf r l 500 r t v i v dd dut v dd open gnd c l 50 pf r l 500 from output under test 2v dd open gnd s1 r l 500 r l = load resistor. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance of z o of the pulse generators.
PCA9655E http://onsemi.com 17 ordering information device package shipping ? PCA9655Edwr2g soic ? 24 (pb ? free) 1000 / tape & reel PCA9655Edtr2g tssop ? 24 (pb ? free) 2500 / tape & reel PCA9655Emttxg wqfn24 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
PCA9655E http://onsemi.com 18 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? a ? ? b ? p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t ? t ? g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 soic ? 24 case 751e ? 04 issue e
PCA9655E http://onsemi.com 19 package dimensions dim min max min max inches millimeters a 7.70 7.90 0.303 0.311 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 13 24 12 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 24x ref k n n 24 lead tssop case 948h issue a
PCA9655E http://onsemi.com 20 package dimensions wqfn24 4x4, 0.5p case 485bg issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.15 pin one reference top view side view bottom view a k d2 e2 c c 0.15 c 0.10 c 0.08 a1 seating plane e 24x note 3 b 24x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.20 0.30 d 4.00 bsc d2 2.00 2.20 e 4.00 bsc e2 2.00 2.20 e 0.50 bsc k 0.20 ??? l 0.30 0.50 7 13 19 24x 0.50 pitch 4.30 0.63 4.30 dimensions: millimeters 0.30 24x 1 l a3 0.20 ref mounting footprint* note 4 a3 detail b 2.26 2.26 1 package outline detail a e/2 l1 detail a l alternate terminal constructions l 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. PCA9655E/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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